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MPC603Eec/d (motorola order number) 5/1999 rev. 2 g522-0268-00 (ibm order number) the powerpc name, the powerpc logotype, powerpc 603, and powerpc 603e are trademarks of international business machines corporation, used by motorola under license from international business machines corporation. flotherm is a registered trademark of flomeric s ltd., uk this document contains information on a new product under development by motorola and ibm. motorola and ibm reserve the right to motorola inc., 1999. all rights reserved. portions hereof international business machines corporation, 1991?999. all rights reserved. change or discontinue this product without notice. advance information powerpc 603e risc microprocessor family: pid6-603e hardware speci?ations the powerpc 603e microprocessor is an implementation of the powerpc family of reduced instruction set computing (risc) microprocessors. in this document, the term ?03e is used as an abbreviation for the phrase, ?owerpc 603e microprocessor? the powerpc 603e microprocessors are available from motorola as MPC603E and from ibm as ppc603e. note that the 603e is implemented in both a 2.5-volt version (pid 0007t powerpc 603e microprocessor, abbreviated as pid7t-603e) and a 3.3-volt version (pid 0006 powerpc 603e microprocessor, abbreviated as pid6-603e). this document describes the pertinent physical characteristics of the pid6-603e. for functional characteristics of the processor, refer to the powerpc 603e risc microprocessor users manual . this document contains the following topics: topic page section 1.1, ?verview 2 section 1.2, ?eatures 3 section 1.3, ?eneral parameters 4 section 1.4, ?lectrical and thermal characteristics 4 section 1.5, ?owerpc 603e microprocessor pin assignments 14 section 1.6, ?owerpc 603e microprocessor pinout listings 16 section 1.7, ?owerpc 603e microprocessor package description 20 section 1.8, ?ystem design information 24 section 1.10, ?rdering information 31 a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 pid6-603e hardware specifications, rev 2 to locate any published errata or updates for this document, refer to the website at http://www.mot.com/powerpc/ or at http://www.chips.ibm.com/products/ppc. 1.1 overview the 603e is a low-power implementation of the powerpc microprocessor family of reduced instruction set computer (risc) microprocessors. the 603e implements the 32-bit portion of the powerpc architecture speci?ation, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and ?ating-point data types of 32 and 64 bits. for 64-bit powerpc microprocessors, the powerpc architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. the 603e provides four software controllable power-saving modes. three of the modes (the nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor. the fourth is a dynamic power management mode that causes the functional units in the 603e to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware. the 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock. instructions can execute out of order for increased performance; however, the 603e makes completion appear sequential. the 603e integrates ?e execution units?n integer unit (iu), a ?ating-point unit (fpu), a branch processing unit (bpu), a load/store unit (lsu), and a system register unit (sru). the ability to execute ?e instructions in parallel and the use of simple instructions with rapid execution times yield high ef?iency and throughput for 603e-based systems. most integer instructions execute in one clock cycle. the fpu is pipelined so a single-precision multiply-add instruction can be issued every clock cycle. the 603e provides independent on-chip, 16-kbyte, four-way set-associative, physically addressed caches for instructions and data, as well as on-chip instruction and data memory management units (mmus). the mmus contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (dtlb and itlb) that provide support for demand-paged virtual memory address translation and variable-sized block translation. the tlbs and caches use a least-recently used (lru) replacement algorithm. the 603e also supports block address translation through the use of two independent instruction and data block address translation (ibat and dbat) arrays of four entries each. effective addresses are compared simultaneously with all four entries in the bat array during block translation. in accordance with the powerpc architecture, if an effective address hits in both the tlb and bat array, the bat translation takes priority. the 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. the 603e interface protocol allows multiple masters to compete for system resources through a central external arbiter. the 603e provides a three-state coherency protocol that supports the exclusive, modi?d, and invalid cache states. this protocol is a compatible subset of the mesi (modi?d/exclusive/shared/invalid) four-state protocol and operates coherently in systems that contain four-state caches. the 603e supports single-beat and burst data transfers for memory accesses, and supports memory-mapped i/o. the 603e uses an advanced, 3.3-v cmos process technology and maintains full interface compatibility with ttl devices. a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 3 1.2 features this section summarizes features of the 603es implementation of the powerpc architecture. major features of the 603e are as follows: high-performance, superscalar microprocessor as many as three instructions issued and retired per clock as many as ?e instructions in execution per clock single-cycle execution for most instructions pipelined fpu for all single-precision and most double-precision operations five independent execution units and two register ?es bpu featuring static branch prediction a 32-bit iu fully ieee 754-compliant fpu for both single- and double-precision operations lsu for data transfer between data cache and gprs and fprs sru that executes condition register (cr), special-purpose register (spr) instructions, and integer add/compare instructions thirty-two gprs for integer operands thirty-two fprs for single- or double-precision operands high instruction and data throughput zero-cycle branch capability (branch folding) programmable static branch prediction on unresolved conditional branches instruction fetch unit capable of fetching two instructions per clock from the instruction cache a six-entry instruction queue that provides lookahead capability independent pipelines with feed-forwarding that reduces data dependencies in hardware 16-kbyte data cache?our-way set-associative, physically addressed; lru replacement algorithm 16-kbyte instruction cache?our-way set-associative, physically addressed; lru replacement algorithm cache write-back or write-through operation programmable on a per page or per block basis bpu that performs cr lookahead operations address translation facilities for 4-kbyte page size, variable block size, and 256-mbyte segment size a 64-entry, two-way set-associative itlb a 64-entry, two-way set-associative dtlb four-entry data and instruction bat arrays providing 128-kbyte to 256-mbyte blocks software table search operations and updates supported through fast-trap mechanism 52-bit virtual address; 32-bit physical address facilities for enhanced system performance a 32- or 64-bit split-transaction external data bus with burst transfers support for one-level address pipelining and out-of-order bus transactions a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4 pid6-603e hardware specifications, rev 2 integrated power management low-power 3.3-volt design internal processor/bus clock multiplier that provides 1/1, 1.5/1, 2/1, 2.5/1, 3/1, 3.5/1, and 4/1 ratios three power saving modes: doze, nap, and sleep automatic dynamic power reduction when internal functional units are idle in-system testability and debugging features through jtag boundary-scan capability 1.3 general parameters the following list provides a summary of the general parameters of the 603e. technology 0.5 cmos, four-layer metal die size 11.67 mm x 8.4 mm (98 mm 2 ) transistor count 2.6 million logic design fully-static package surface mount 240-pin ceramic quad ?t pack (cqfp) or 255-pin ceramic ball grid array (cbga) power supply 3.3 ?5% v dc 1.4 electrical and thermal characteristics this section provides the ac and dc electrical speci?ations and thermal characteristics for the 603e. 1.4.1 dc electrical characteristics the tables in this section describe the 603e dc electrical characteristics. table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings characteristic symbol value unit core supply voltage vdd ?.3 to 4.0 v pll supply voltage avdd ?.3 to 4.0 v i/o supply voltage ovdd ?.3 to 4.0 v input voltage v in ?.3 to 5.5 v storage temperature range t stg ?5 to 150 ? notes: 1. functional operating conditions are given in table 2. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution : v in must not exceed ovdd by more than 2.5 v at any time including during power-on reset. 3. caution : ovdd must not exceed vdd/avdd by more than 2.5 v at any time including during power-on reset. 4. caution : vdd/avdd must not exceed ovdd by more than 0.4 v at any time including during power-on reset. a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 5 table 2 provides the recommended operating conditions for the 603e. table 3 provides the packages thermal characteristics for the 603e. table 4 provides the dc electrical characteristics for the 603e. table 2. recommended operating conditions characteristic symbol value unit notes core supply voltage vdd 3.3 ?165mv v pll supply voltage avdd 3.3 ?165mv v i/o supply voltage ovdd 3.3 ?165mv v input voltage v in -0.3 to 5.5 v die-junction temperature t j 0 to 105 ? 2 notes : 1. these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 2. the extended temperature parts have die-junction temperature of -40 to 105 ?. table 3. package thermal characteristics characteristic symbol value rating wire-bond cqfp package die junction-to-case thermal resistance (typical) q jc 2.2 ?/w wire-bond cqfp package die junction-to-lead thermal resistance (typical) q jb 18.0 ?/w cbga package die junction-to-case thermal resistance (typical) q jc 0.08 ?/w cbga package die junction-to-ball thermal resistance (typical) q jb 2.8 ?/w note: refer to section 1.8, ?ystem design information, for more details about thermal management. table 4. dc electrical specifications at recommended operating conditions. see table 2. characteristic symbol min max unit notes input high voltage (all inputs except sysclk) v ih 2.0 5.5 v input low voltage (all inputs except sysclk) v il -0.3 0.8 v sysclk input high voltage cv ih 2.4 5.5 v sysclk input low voltage cv il -0.3 0.4 v input leakage current, v in = 3.465 v v in = 5.5 v i in ?0a 1 i in 245 ? 1 hi-z (off-state) leakage current, v in = 3.465 v v in = 5.5 v i tsi ?0a 1 i tsi 245 ? 1 output high voltage, i oh = ? ma v oh 2.4 v 1 output low voltage, i ol = 14 ma v ol 0.4 v a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 pid6-603e hardware specifications, rev 2 table 5 provides the power consumption for the 603e. capacitance, v in = 0 v, f = 1 mhz (excludes ts , abb , dbb , and ar tr y ) c in 10.0 pf 2 capacitance, v in = 0 v, f = 1 mhz (for ts , abb , dbb , and ar tr y ) c in 15.0 pf 2 notes: 1. excludes test signals (lssd_mode, l1_tstclk, l2_tstclk) and jtag signals. 2. capacitance is periodically sampled rather than 100% tested. table 5. power consumption at recommended operating conditions. see table 2. cpu clock: sysclk processor (cpu) frequency unit notes 100 mhz 133.33 mhz full-on mode (dpm enabled) typical max. 3.2 4.2 w 1, 3 4.0 5.3 w 1, 2 doze mode typical 1.0 1.3 w 1, 2 nap mode typical 70 85 mw 1, 2 sleep mode typical 40 50 mw 1, 2 sleep mode?ll disabled typical 5 6 mw 1, 2 sleep mode?ll and sysclk disabled typical 3 3 mw 1, 2 notes: 1. these values apply for all valid bus ratios (pll_cfg[0?] settings). the values do not include i/o supply power (ovdd) or pll supply power (avdd). ovdd power is system dependent, but is typically <10% of vdd power. worst-case power consumption for avdd = 15 mw. 2. maximum power is measured at vdd = 3.465 v using a worst-case instruction mix. 3. typical power is an average value measured at vdd = avdd = ovdd = 3.3 v in a system executing typical applications and benchmark sequences table 4. dc electrical specifications (continued) at recommended operating conditions. see table 2. characteristic symbol min max unit notes a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 7 1.4.2 ac electrical characteristics this section provides the ac electrical characteristics for the 603e. after fabrication, parts are sorted by maximum processor core frequency as shown in section 1.4.2.1, ?lock ac speci?ations?and tested for conformance to the ac speci?ations for that frequency. these speci?ations are for 100 and 133.33 mhz processor core frequencies. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg[0?] signals. parts are sold by maximum processor core frequency; see section 1.10, ?rdering information. 1.4.2.1 clock ac speci?ations table 6 provides the clock ac timing speci?ations as de?ed in figure 1. table 6. clock ac timing specifications at recommended operating conditions. see table 2. num characteristic 100 mhz 133.33 mhz unit notes min max min max processor frequency 50 100 50 133.33 mhz 1 vco frequency 100 266.66 100 266.66 mhz 1 sysclk (bus) frequency 16.67 66.67 16.67 66.67 mhz 1 sysclk cycle time 15.0 60.0 15.0 60.0 ns 2,3 sysclk rise and fall time 2.0 2.0 ns 2 4 sysclk duty cycle measured at 1.4 v 40.0 60.0 40.0 60.0 % 3 sysclk jitter ?50 ?50 ps 4 internal pll relock time 100 100 m s 3, 5 notes: 1. caution : the sysclk frequency and pll_cfg[0?] settings must be chosen such that the resulting sysclk (bus) frequency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0?] signal description in section 1.8, ?ystem design information, for valid pll_cfg[0?] settings. 2. rise and fall times for the sysclk input are measured from 0.4 v to 2.4 v. 3. timing is guaranteed by design and characterization, and is not tested. 4. cycle-to-cycle jitter, and is guaranteed by design. 5. relock timing is guaranteed by design and characterization, and is not tested. pll-relock time is the maximum amount of time required for pll lock after a stable vdd and sysclk are reached during the power-on reset sequence. this speci?ation also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 pid6-603e hardware specifications, rev 2 figure 1 provides the sysclk input timing diagram. figure 1. sysclk input timing diagram 1.4.2.2 input ac speci?ations table 7 provides the input ac timing speci?ations for the 603e as de?ed in figure 2 and figure 3. table 7. input ac timing specifications at recommended operating conditions. see table 2. num characteristic 100 mhz 133.33 mhz unit notes min max min max 10a address/data/transfer attribute inputs valid to sysclk (input setup) 3.0 3.0 ns 2 10b all other inputs valid to sysclk (input setup) 5.0 5.0 ns 3 10c mode select inputs valid to hreset (input setup) (for dr tr y , qa ck and tlbisync ) 8*t sysclk 8*t sysclk ns 4,5,6, 7 11a sysclk to address/data/transfer attribute inputs invalid (input hold) 1.0 1.0 ns 2 11b sysclk to all other inputs invalid (input hold) 1.0 1.0 ns 3 11c hreset to mode select inputs invalid (input hold) (for dr tr y , qa ck , and tlbisync ) 0 0 ns 4,6,7 notes: 1. all input speci?ations are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the 1.4 v of the rising edge of the input sysclk (see figure 2). both input and output timings are measured at the pin. 2. address/data/transfer attribute input signals are composed of the following?[0?1], ap[0?], tt[0?], tc[0?], tbst , tsiz[0?], gbl , dh[0?1], dl[0?1], dp[0?]. 3. all other input signals are composed of the following?ts , abb , dbb , ar tr y , bg , aa ck , dbg , dbw o , t a , dr tr y , tea , dbdis , hreset , sreset , int , smi , mcp , tben, qa ck , tlbisync . 4. the setup and hold time is with respect to the rising edge of hreset (see figure 3). 5. t sysclk is the period of the external clock (sysclk) in nanoseconds. 6. these values are guaranteed by design, and are not tested. 7. this speci?ation is for con?uration mode select only. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. vm cvil cvih sysclk vm = midpoint voltage (1.4 v) 2 3 1 44 vm vm a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 9 figure 2 provides the input timing diagram for the 603e. figure 2. input timing diagram figure 3 provides the mode select input timing diagram for the 603e. figure 3. mode select input timing diagram vm sysclk all inputs vm = midpoint voltage (1.4 v) 10a 10b 11a 11b mode pins hreset vm vm = midpoint voltage (1.4 v) 10c 11c a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 pid6-603e hardware specifications, rev 2 1.4.2.3 output ac speci?ations table 8 provides the output ac timing speci?ations for the 603e as de?ed in figure 4. table 8. output ac timing specifications 1 at recommended operating conditions. see table 2., c l = 50 pf 2 num characteristic 100 mhz 133.33 mhz unit notes min max min max 12 sysclk to output driven (output enable time) 1.0 1.0 ns 13a sysclk to output valid (5.5 v to 0.8 v?s , abb , ar tr y , dbb ) 11.0 11.0 ns 4 13b sysclk to output valid (ts , abb , ar tr y , dbb ) 10.0 10.0 ns 6 14a sysclk to output valid (5.5 v to 0.8 v?ll except ts , abb , ar tr y , dbb ) 13.0 13.0 ns 4 14b sysclk to output valid (all except ts , abb , ar tr y , dbb ) 11.0 11.0 ns 6 15 sysclk to output invalid (output hold) 1.5 1.5 ns 3 16 sysclk to output high impedance (all except ar tr y , abb , dbb ) 9.5 9.5 ns 17 sysclk to abb , dbb , high impedance after precharge 1.2 1.2 t sysclk 5,7 18 sysclk to ar tr y high impedance before precharge 9.0 9.0 ns 19 sysclk to ar tr y precharge enable 0.2 * t sysclk + 1.0 0.2 * t sysclk + 1.0 ns 3,5,8 20 maximum delay to ar tr y precharge 1.2 1.2 t sysclk 5,8 21 sysclk to ar tr y high impedance after precharge 2.25 2.25 t sysclk 5,8 notes: 1. all output speci?ations are measured from the 1.4 v of the rising edge of sysclk to the ttl level (0.8 v or 2.0 v) of the signal in question. both input and output timings are measured at the pin (see figure 4). 2. all maximum timing speci?ations assume c l = 50 pf. 3. this minimum parameter assumes c l = 0 pf. 4. sysclk to output valid (5.5 v to 0.8 v) includes the extra delay associated with discharging the external voltage from 5.5 v to 0.8 v instead of from vdd to 0.8 v (5 v cmos levels instead of 3.3 v cmos levels). 5. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 6. output signal transitions from gnd to 2.0 v or vdd to 0.8 v. 7. nominal precharge width for abb and dbb is 0.5 t sysclk . 8. nominal precharge width for ar tr y is 1.0 t sysclk . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 11 figure 4 provides the output timing diagram for the 603e. figure 4. output timing diagram 1.4.3 jtag ac timing speci?ations table 9 provides the jtag ac timing speci?ations as de?ed in figure 5 through figure 8. table 9. jtag ac timing specifications (independent of sysclk) at recommended operating conditions. see table 2. c l = 50 pf num characteristic min max unit notes tck frequency of operation 0 16 mhz 1 tck cycle time 62.5 ns 2 tck clock pulse width measured at 1.4 v 25 ns 3 tck rise and fall times 0 3 ns 4 trst setup time to tck rising edge 13 ns 1 5 trst assert time 40 ns 6 boundary-scan input data setup time 6 ns 2 7 boundary-scan input data hold time 27 ns 2 8 tck to output data valid 4 25 ns 3 9 tck to output high impedance 3 24 ns 3 sysclk 12 14 13 15 16 16 ts ar tr y abb , dbb vm vm vm = midpoint voltage (1.4 v) 15 vm 13 20 18 17 21 19 all outputs (except ts , abb , dbb , artry ) a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
12 pid6-603e hardware specifications, rev 2 figure 5 provides the jtag clock input timing diagram. figure 5. jtag clock input timing diagram figure 6 provides the trst timing diagram . figure 6. trst timing diagram 10 tms, tdi data setup time 0 ns 11 tms, tdi data hold time 25 ns 12 tck to tdo data valid 4 24 ns 13 tck to tdo high impedance 3 15 ns notes: 1. trst is an asynchronous signal. the setup time is for test purposes only. 2. non-test signal input timing with respect to tck. 3. non-test signal output timing with respect to tck. table 9. jtag ac timing specifications (independent of sysclk) (continued) at recommended operating conditions. see table 2. c l = 50 pf num characteristic min max unit notes tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage (1.4 v) 4 5 trst tck vm a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 13 figure 7 provides the boundary-scan timing diagram. figure 7. boundary-scan timing diagram figure 8 provides the test access port timing diagram. figure 8. test access port timing diagram 6 7 input data valid 8 9 8 output data valid output data valid tck data inputs data outputs data outputs data outputs vm vm 10 11 input data valid 12 13 12 output data valid output data valid tck tdi, tms tdo tdo tdo vm vm a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
14 pid6-603e hardware specifications, rev 2 1.5 powerpc 603e microprocessor pin assignments the following sections contain the pinout diagrams for the 603e. note that the 603e is offered in both ceramic quad ?t pack (cqfp) and ceramic ball grid array (cbga) packages. 1.5.1 pinout diagram for the cqfp package figure 9 contains the pinout diagram of the cqfp package for the 603e. figure 9. pinout diagram for the cqfp package gbl a1 a3 vdd a5 a7 a9 ognd gnd ovdd a11 a13 a15 vdd a17 a19 a21 ognd gnd ovdd a23 a25 a27 vdd dbw o dbg bg aa ck gnd a29 qreq ar tr y ognd vdd ovdd abb a31 dp0 gnd dp1 dp2 dp3 ognd vdd ovdd dp4 dp5 dp6 gnd dp7 dl23 dl24 ognd ovdd dl25 dl26 dl27 dl28 vdd ognd tt4 a0 a2 vdd a4 a6 a8 ovdd gnd ognd a10 a12 a14 vdd a16 a18 a20 ovdd gnd ognd a22 a24 a26 vdd dr tr y t a tea dbdis gnd a28 cse1 ts ovdd vdd ognd dbb a30 dl0 gnd dl1 dl2 dl3 ovdd vdd ognd dl4 dl5 dl6 gnd dl7 dl8 dl9 ovdd ognd dl10 dl11 dl12 dl13 vdd ovdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 ovdd gnd ognd ci wt qa ck tben tlbisync rsr v ap0 ap1 ovdd ognd ap2 ap3 cse0 tc0 tc1 ovdd clk_out ognd br ape dpe c kstp_out ckstp _in hreset pll_cfg0 sysclk pll_cfg1 pll_cfg2 avdd pll_cfg3 vdd gnd lssd_mode l1_tstclk l2 _tstclk trst tck tms tdi tdo tsiz0 tsiz1 tsiz2 ovdd ognd tbst tt0 tt1 sreset int smi mcp tt2 tt3 ovdd gnd ognd 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 ovdd dl29 dl30 dl31 gnd dh31 dh30 dh29 ognd ovdd dh28 dh27 dh26 dh25 dh24 dh23 ognd dh22 ovdd dh21 dh20 dh19 dh18 dh17 dh16 ognd dh15 ovdd dh14 dh13 dh12 dh11 dh10 dh9 ognd ovdd dh8 dh7 dh6 dl22 dl21 dl20 ognd ovdd dl19 dl18 dl17 dh5 dh4 dh3 ognd ovdd dh2 dh1 dh0 gnd dl16 dl15 dl14 ognd 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 1 top view a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 15 1.5.2 pinout diagram for the cbga package figure 10 (in part a) shows the pinout of the cbga package as viewed from the top surface. part b shows the side profile of the cbga package to indicate the direction of the top surface view. part a figure 10. pinout of the cbga package as viewed from the top surface a b c d e f g h j k l m n p r t 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 not to scale view part b die substrate assembly encapsulant a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
16 pid6-603e hardware specifications, rev 2 1.6 powerpc 603e microprocessor pinout listings the following sections contain the pinout listings for the 603e cqfp and cbga packages. 1.6.1 pinout listing for the cqfp package table 10 provides the pinout listing for the 603e cqfp package. table 10. pinout listing for the 240-pin cqfp package signal name pin number active i/o a[0?1] 179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, 11, 169, 12, 168, 13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22, 158, 23, 151, 30, 144, 37 high i/o aa ck 28 low input abb 36 low i/o ap[0?] 231, 230, 227, 226 high i/o ape 218 low output ar tr y 32 low i/o avdd 209 high input bg 27 low input br 219 low output ci 237 low output clk_out 221 output ckstp_in 215 low input ckstp_out 216 low output cse[0?] 1 225, 150 high output dbb 145 low i/o dbdis 153 low input dbg 26 low input dbw o 25 low input dh[0?1] 115, 114, 113, 110, 109, 108, 99, 98, 97, 94, 93, 92, 91, 90, 89, 87, 85, 84, 83, 82, 81, 80, 78, 76, 75, 74, 73, 72, 71, 68, 67, 66 high i/o dl[0?1] 143, 141, 140, 139, 135, 134, 133, 131, 130, 129, 126, 125, 124, 123, 119, 118, 117, 107, 106, 105, 102, 101, 100, 51, 52, 55, 56, 57, 58, 62, 63, 64 high i/o dp[0?] 38, 40, 41, 42, 46, 47, 48, 50 high i/o dpe 217 low output dr tr y 156 low input gbl 1 low i/o gnd 9, 19, 29, 39, 49, 65, 116, 132, 142, 152, 162, 172, 182, 206, 239 low input hreset 214 low input int 188 low input a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 17 lssd_mode 2 205 low input l1_tstclk 2 204 input l2_tstclk 2 203 input mcp 186 low input ognd 8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228, 238 low input ovdd 3 10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104, 112, 121, 128, 138, 148, 163, 173, 183, 194, 222, 229, 240 high input pll_cfg[0?] 213, 211, 210, 208 high input qa ck 235 low input qreq 31 low output rsr v 232 low output smi 187 low input sreset 189 low input sysclk 212 input t a 155 low input tben 234 high input tbst 192 low i/o tc[0?] 224, 223 high output tck 201 input tdi 199 high input tdo 198 high output tea 154 low input tlbisync 233 low input tms 200 high input trst 202 low input tsiz[0?] 197, 196, 195 high i/o ts 149 low i/o tt[0?] 191, 190, 185, 184, 180 high i/o vdd 3 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177, 207 high input wt 236 low output notes: 1. there are two cse signals in the 603e?se0 and cse1. the xa ts signal in the powerpc 603 microprocessor is replaced by the cse1 signal in 603e. 2. these are test signals for factory use only and must be pulled up to ovdd for normal machine operation. 3. ovdd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. future members of the 603 family may use different ovdd and vdd input levels. table 10. pinout listing for the 240-pin cqfp package (continued) signal name pin number active i/o a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
18 pid6-603e hardware specifications, rev 2 1.6.2 pinout listing for the cbga package table 11 provides the pinout listing for the 603e cbga package. table 11. pinout listing for the 255-pin cbga package signal name pin number active i/o a[0?1] c16, e04, d13, f02, d14, g01, d15, e02, d16, d04, e13, go2, e15, h01, e16, h02, f13, j01, f14, j02, f15, h03, f16, f04, g13, k01, g15, k02, h16, m01, j15, p01 high i/o aa ck l02 low input abb k04 low i/o ap[0?] c01, b04, b03, b02 high i/o ape a04 low output ar tr y j04 low i/o avdd a10 bg l01 low input br b06 low output ci e01 low output ckstp_in d08 low input ckstp_out a06 low output clk_out d07 output cse[0?] b01, b05 high output dbb j14 low i/o dbg n01 low input dbdis h15 low input dbw o g04 low input dh[0?1] p14, t16, r15, t15, r13, r12, p11, n11, r11,t12, t11, r10, p09, n09, t10, r09, t09, p08, n08, r08, t08, n07, r07, t07, p06, n06, r06, t06, r05, n05, t05, t04 high i/o dl[0?1] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, n10, p13, n12, t13, p03, n03, n04, r03, t01, t02, p04, t03, r04 high i/o dp[0?] m02, l03, n02, l04, r01, p02, m04, r02 high i/o dpe a05 low output dr tr y g16 low input gbl f01 low i/o gnd c05, c12, e03, e06, e08, e09, e11, e14, f05, f07, f10, f12, g06, g08, g09, g11, h05, h07, h10, h12, j05, j07, j10, j12, k06, k08, k09, k11, l05, l07, l10, l12, m03, m06, m08, m09, m11, m14, p05, p12 hreset a07 low input int b15 low input l1_tstclk 1 d11 input a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 19 l2_tstclk 1 d12 input lssd_mode 1 b10 low input mcp c13 low input nc b07, b08, c03, c06, c08, d05, d06, f03, h04, j16 low input ovdd c07, e05, e07, e10, e12, g03, g05, g12, g14, k03, k05, k12, k14, m05, m07, m10, m12, p07, p10 pll_cfg[0?] a08, b09, a09, d09 high input qa ck d03 low input qreq j03 low output rsr v d01 low output smi a16 low input sreset b14 low input sysclk c09 input t a h14 low input tben c02 high input tbst a14 low i/o tc[0?] a02, a03 high output tck c11 input tdi a11 high input tdo a12 high output tea h13 low input tlbisync c04 low input tms b11 high input trst c10 low input ts j13 low i/o tsiz[0?] a13, d10, b12 high i/o tt[0?] b13, a15, b16, c14, c15 high i/o wt d02 low output vdd 2 f06, f08, f09, f11, g07, g10, h06, h08, h09, h11, j06, j08, j09, j11, k07, k10, l06, l08, l09, l11 notes: 1. these are test signals for factory use only and must be pulled up to ovdd for normal machine operation. 2. ovdd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. future members of the 603 family may use different ovdd and vdd input levels. table 11. pinout listing for the 255-pin cbga package (continued) signal name pin number active i/o a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
20 pid6-603e hardware specifications, rev 2 1.7 powerpc 603e microprocessor package description the following sections provide the package parameters and the mechanical dimensions for the 603e. 1.7.1 cqfp package description the following sections provide the package parameters and mechanical dimensions for the motorola cqfp package. 1.7.1.1 package parameters the package parameters are as provided in the following list. the package type is 32 mm x 32 mm, 240-pin ceramic quad ?t pack. package outline 32 mm x 32 mm interconnects 240 pitch 0.5 mm a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 21 1.7.1.2 mechanical dimensions of the cqfp package figure 11 shows the mechanical dimensions of the motorola cqfp package. figure 11. mechanical dimensions of the wire-bond cqfp package *reduced pin count shown for clarity. 60 pins per side min. max. a 30.86 31.75 b 34.6 bsc c 3.75 4.15 d 0.5 bsc e 0.18 0.30 f 3.10 3.90 g 0.13 0.175 h 0.45 0.55 j 0.25 aa 1.80 ref ab 0.95 ref q 126 q 217 r 0.15 ref ? ab q i r r aa q 2 h pin 240 c a b pin 1 de *not to scale g f j die wire bonds ceramic body alloy 42 leads notes : 1. bsc?etween standard centers. 2. all measurements in mm. a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
22 pid6-603e hardware specifications, rev 2 1.7.2 cbga package description the following sections provide the package parameters and mechanical dimensions for the cbga package. 1.7.2.1 package parameters the package parameters are as provided in the following list. the package type is 21 x 21 mm, 255-pin ceramic ball grid array (cbga). package outline 21 mm interconnects 255 pitch 1.27 mm minimum module height 2.45 mm maximum module height 3.00 mm ball diameter 0.89 mm (35 mil) a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 23 1.7.2.2 mechanical dimensions of the cbga package figure 12 provides the mechanical dimensions and bottom surface nomenclature of the cbga package. figure 12. mechanical dimensions and bottom surface nomenclature of the cbga package notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 0.200 f t 255x a 2x a1 corner p n 0.200 2x ?e 12345678910111213141516 a b c d e f g h j k l m n p r t e 0.300 t 0.150 d c h 0.150 t b ?f k k g s s s s ?t dim millimeters inches min max min max a 21.000 bsc 0.827 bsc b 21.000 bsc 0.827 bsc c 2.450 3.000 0.096 0.118 d 0.820 0.930 0.032 0.036 g 1.270 bsc 0.050 bsc h 0.790 0.990 0.031 0.039 k 0.635 bsc 0.025 bsc n 5.000 16.000 0.197 0.630 p 5.000 16.000 0.197 0.630 a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
24 pid6-603e hardware specifications, rev 2 1.8 system design information this section provides electrical and thermal design recommendations for successful application of the 603e. 1.8.1 pll con?uration the 603e pll is con?ured by the pll_cfg[0?] signals. for a given sysclk (bus) frequency, the pll con?uration signals set the internal cpu and vco frequency of operation. the pll con?uration for the 603e is shown in table 12 for nominal frequencies. table 12. powerpc 603e microprocessor pll configuration pll_cfg[0?] cpu frequency in mhz (vco frequency in mhz) bus-to- core multiplier core -to- vco multiplier bus 16.67 mhz bus 20 mhz bus 25 mhz bus 33.33 mhz bus 40 mhz bus 50 mhz bus 60 mhz bus 66.67 mhz 0000 1x 2x 50 (100) 60 (120) 66.67 (133) 0001 1x 4x 50 (200) 60 (240) 66.67 (266) 1100 1.5x 2x 50 (100) 60 (120) 75 (150) 90 (180) 100 (200) 0100 2x 2x 66.67 (133) 80 (160) 100 (200) 120 (240) 133.33 (266) 0101 2x 4x 50 (200) 66.67 (266) 0110 2.5x 2x 50 (100) 62.5 (125) 83.33 (166) 100 (200) 125 (250) 1000 3x 2x 50 (100) 60 (120) 75 (150) 100 (200) 120 (240) 1110 3.5x 2x 58.4 (117) 70 (140) 87.5 (175) 116.67 (233) 1010 4x 2x 66.67 (133) 80 (160) 100 (200) 133.33 (266) 0011 pll bypass 1111 clock off notes: 1. pll_cfg[0?] settings not listed are reserved. 2. the sample bus-to-core frequencies shown are for reference only. some pll con?urations may select bus, core, or vco frequencies which are not useful, not supported, or not tested for by the 603e; see section 1.4.2.1, ?lock ac speci?ations, for valid sysclk and vco frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. note : the ac timing speci?ations given in this document do not apply in pll-bypass mode. 4. in clock-off mode, no clocking occurs inside the 603e regardless of the sysclk input. a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 25 1.8.2 pll power supply filtering the avdd power signal is provided on the 603e to provide power to the clock generation phase-locked loop. to ensure stability of the internal clock, the power supplied to the avdd input signal should be ?tered using a circuit similar to the one shown in figure 13. the circuit should be placed as close as possible to the avdd pin to ensure it ?ters out as much noise as possible. figure 13. pll power supply filter circuit 1.8.3 decoupling recommendations due to the 603es dynamic power management feature, large address and data buses, and high operating frequencies, the 603e can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the 603e system, and the 603e itself requires a clean, tightly regulated source of power. therefore, it is strongly recommended that the system designer place at least one decoupling capacitor at each vdd and ovdd pin of the 603e. it is also recommended that these decoupling capacitors receive their power from separate vdd, ovdd, and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should vary in value from 220 pf to 10 m f to provide both high- and low-frequency ?tering, and should be placed as close as possible to their associated vdd or ovdd pin. suggested values for the vdd pins?20 pf (ceramic), 0.01 ? (ceramic), and 0.1 ? (ceramic). suggested values for the ovdd pins?.01 ? (ceramic), 0.1 ? (ceramic), and 10 ? (tantalum). only smt (surface mount technology) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd and ovdd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should also have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?00 ? (avx tps tantalum) or 330 ? (avx tps tantalum). 1.8.4 connection recommendations to ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to vdd. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. 1.8.5 pull-up resistor requirements the 603e requires high-resistive (weak: 10 kohms) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the 603e or other bus master. these signals are?s , abb , dbb , ar tr y . in addition, the 603e has three open-drain style outputs that require pull-up resistors (weak or stronger: 4.7 kohms?0 kohms) if they are used by the system. these signals are?pe , dpe , and ckstp_out . vdd avdd 10 w 10 ? 0 . 1 ? gnd a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
26 pid6-603e hardware specifications, rev 2 during inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may ?at in the high-impedance state for relatively long periods of time. since the 603e must continually monitor these signals for snooping, this ?at condition may cause excessive power draw by the input receivers on the 603e. it is recommended that these signals be pulled up through weak (10 kohms) pull-up resistors or restored in some manner by the system. the snooped address and transfer attribute inputs are?[0?1], ap[0?], tt[0?], tbst , tsiz[0?], and gbl . the data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. 1.8.6 thermal management information this section provides thermal management information for the ceramic quad-?t package (cqfp) and the ceramic ball grid array (cbga) package for air-cooled applications. proper thermal control design is primarily dependent upon the system-level design?he heat sink, air?w and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (cbga package); see figure 14. this spring force should not exceed 5.5 pounds of force. figure 14. package exploded cross-sectional view with several heat sink options the board designer can choose between several types of heat sinks to place on the 603e. there are several commercially-available heat sinks for the 603e provided by the following vendors: chip coolers inc. 800-227-0254 (usa/canada) 333 strawberry field rd. 401-739-7600 warwick, ri 02887-6979 international electronic research corporation (ierc) 818-842-7277 135 w. magnolia blvd. burbank, ca 91502 adhesive wb/c4-cqfp package or thermal interface material heat sink cbga package heat sink clip printed-circuit board option a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 27 thermalloy 214-243-4321 2021 w. valley view lane p.o. box 810839 dallas, tx 75731 wake?ld engineering 617-245-5900 60 audubon rd. wake?ld, ma 01880 aavid engineering 603-528-3400 one kool path laconia, nh 03247-0440 ultimately, the ?al selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 1.8.6.1 internal package conduction resistance for this packaging technology the intrinsic thermal conduction resistance (shown in table 3) versus the external thermal resistance paths are shown in figure 15 for a package with an attached heat sink mounted to a printed-circuit board. figure 15. package with heat sink mounted to a printed-circuit board 1.8.6.2 adhesives and thermal interface materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 16 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, ?roether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease signi?antly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. external resistance external resistance internal resistance (note the internal versus external package resistance) radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
28 pid6-603e hardware specifications, rev 2 heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 14). this spring force should not exceed 5.5 pounds of force. therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. of course, the selection of any thermal interface material depends on many factors?hermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. figure 16. thermal performance of select thermal interface material the board designer can choose between several types of thermal interface. heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. there are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: dow-corning corporation 517-496-4000 dow-corning electronic materials po box 0997 midland, mi 48686-0997 chomerics, inc. 617-935-4850 77 dragon court woburn, ma 01888-4850 0 0.5 1 1.5 2 0 1020 304050607080 graphite/oil sheet (0.005 inch) silicone sheet (0.006 inch) floroether oil sheet (0.007 inch) synthetic grease bare joint specific thermal resistance (kin 2 /w) contact pressure (psi) contact pressure (psi) specific thermal resistance (kin 2 /w) a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 29 thermagon inc. 216-741-7659 3256 west 25th street cleveland, oh 44109-1668 loctite corporation 860-571-5100 1001 trout brook crossing rocky hill, ct 06067 ai technology (e.g. eg7655) 609-882-2332 1425 lower ferry rd. trent, nj 08618 the following section provides a heat sink selection example using one of the commercially available heat sinks. 1.8.6.3 heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t a + t r + ( q jc + q int + q sa ) * p d where : t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet q jc is the junction-to-case thermal resistance q int is the adhesive or interface material thermal resistance q sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation the die-junction temperatures (t j ) should be maintained less than the value speci?d in table 2. the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 ?. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 ?. the thermal resistance of the thermal interface material ( q int ) is typically about 1 ?/w. assuming a t a of 30 ?, a t r of 5 ?, a cqfp package q jc = 2.2, and a power consumption (p d ) of 4.5 watts, the following expression for t j is obtained: die-junction temperature: t j = 30 ? + 5 ? + (2.2 ?/w + 1.0 ?/w + r sa ) * 4.5 w for a thermalloy heat sink #2328b, the heat sink-to-ambient thermal resistance (r sa ) versus air?w velocity is shown in figure 17. a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
30 pid6-603e hardware specifications, rev 2 figure 17. thermalloy #2328b heat sink-to-ambient thermal resistance versus airflow velocity assuming an air velocity of 0.5 m/s, we have an effective r sa of 7 ?/w, thus t j = 30? + 5? + (2.2 ?/w +1.0 ?/w + 7 ?/w) * 4.5 w, resulting in a die-junction temperature of approximately 81 ? which is well within the maximum operating temperature of the component. other heat sinks offered by chip coolers, ierc, thermalloy, wake?ld engineering, and aavid engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air ?w. though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common ?ure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat ?w. the ?al die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the ?al operating die-junction temperature?ir?w, board population (local heat ?x of adjacent components), heat sink ef?iency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. to expedite system-level thermal analysis, several ?ompact thermal-package models are available within flotherm? these are available upon request. 1 2 3 4 5 6 7 8 0 0.5 1 1.5 2 2.5 3 3.5 thermalloy #2328b pin-fin heat sink (25 x 28 x 15 mm) heat sink thermal resistance ( c/w) approach airflow velocity (m/s) approach airflow velocity (m/s) heat sink thermal resistance (?/w) a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
pid6-603e hardware specifications, rev 2 31 1.9 document revision history 1.10 ordering information this section provides the part numbering nomenclature for the 603e. note that the individual part numbers correspond to a maximum processor core frequency. for available frequencies, contact your local motorola or ibm sales of?e. 1.10.1 motorola part number key figure 18 provides the motorola part numbering nomenclature for the 603e. in addition to the processor frequency, the part numbering scheme also consists of a part modi?r and application modi?r. the part modi?r indicates any enhancement(s) in the part from the original production design. the bus divider may specify special bus frequencies or application conditions. each part number also contains a revision code. this refers to the die mask revision number and is speci?d in the part numbering scheme for identi?ation purposes only. figure 18. motorola part number key table 13. document revision history document revision substantive change(s) rev 2 in table 6, the minimun processor frequency for the 100 mhz and the 133 mhz parts was changed to 50 mhz. the maximum vco frequency was changed to 266.66 mhz on and the minimum vco frequency on the 133 mhz part was changed to 100 mhz. in table 12 the cpu and vco frequencies were changed to correspond to the valid clock speci?ations as shown in table 6. table 2 includes notes on extended temperature parts. mpc 603 e xx xxx x x product code part identifier part modifier application modifier max. internal processor speed (e = enhanced) (fe = wire-bond cqfp, package rx = ceramic ball grid array) revision level (contact motorola sales office) (t = ext. temp.spec, -40-105? t j ) (l = full spec, 0-105? t j ) a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mfax and ec603e are trademarks of motorola, inc. the powerpc name, the powerpc logotype, and powerpc 603 are trademarks of international business machines corporation used by m otorola under license from international business machines corporation. flotherm is a registered trademark of flomerics ltd., uk. information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. ther e are no express or implied copyright licenses granted hereunder to design or fabricate powerpc integrated circuits or integrated circuits based on the inf ormation in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? ypical?parameters can and do vary in different applications. all operating parameters, including ?ypicals?must be validated for each customer application by custo mer? technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any o ther application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorol a products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affi liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any clai m of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the desig n or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer. motorola literature distribution centers : usa/europe: motorola literature distribution; p.o. box 5405; denver, colorado 80217; tel.: 1-800-441-2447 or 1-303-675-2140; world wide web address: http://ldc.nmd.com/ japan : nippon motorola ltd spd, strategic planning of?e 4-32-1, nishi-gotanda shinagawa-ku, tokyo 141, japan tel.: 81-3-5487-8488 asia/pacific : motorola semiconductors h.k. ltd silicon harbour centre 2, dai king street tai po industrial estate tai po, new territories, hong kong mfax : rmfax0@email.sps.mot.com; touchtone 1-602-244-6609; us & canada only (800) 774-1848; world wide web address : http://sps.motorola.com/mfax internet : http://motorola.com/sps technical information : motorola inc. sps customer support center 1-800-521-6274; electronic mail address: crc@wmkmail.sps.mot.com. document comments : fax (512) 895-2638, attn: risc applications engineering. world wide web addresses : http://www.motorola.com/powerpc http://www.motorola.com/netcomm http://www.motorola.com/hpesd MPC603Eec/d a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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